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MC100EP195B 3.3V ECL Programmable Delay Chip
Descriptions
The MC100EP195B is a Programmable Delay Chip (PDC) designed primarily for clock deskewing and timing adjustment. It provides variable delay of a differential NECL/PECL input transition. The delay section consists of a programmable matrix of gates and multiplexers as shown in the logic diagram, Figure 2. The delay increment of the EP195B has a digitally selectable resolution of about 10 ps and a net range of up to 10.2 ns. The required delay is selected by the 10 data select inputs D[9:0] values and controlled by the LEN (pin 10). A LOW level on LEN allows a transparent LOAD mode of real time delay values by D[9:0]. A LOW to HIGH transition on LEN will LOCK and HOLD current values present against any subsequent changes in D[10:0]. The approximate delay values for varying tap numbers correlating to D0 (LSB) through D9 (MSB) are shown in Table 6 and Figure 3. The IN/IN inputs can accept LVPECL (SE of Diff), or LVDS level signals. Because the EP195B is designed using a chain of multiplexers it has a fixed minimum delay of 2.2 ns. An additional pin D10 is provided for controlling Pins 14 and 15, CASCADE and CASCADE, also latched by LEN, in cascading multiple PDCs for increased programmable range. The cascade logic allows full control of multiple PDCs. Switching devices from all "1" states on D[0:9] with SETMAX LOW to all "0" states on D[0:9] with SETMAX HIGH will increase the delay equivalent to "D0", the minimum increment. Select input pins D[10:0] may be threshold controlled by combinations of interconnects between VEF (pin 7) and VCF (pin 8) for LVCMOS, ECL, or LVTTL level signals. For LVCMOS input levels, leave VCF and VEF open. For ECL operation, short VCF and VEF (Pins 7 and 8). For LVTTL level operation, connect a 1.5 V supply reference to VCF and leave open VEF pin. The 1.5 V reference voltage to VCF pin can be accomplished by placing a 2.2 kW resistor between VCF and VEE for a 3.3 V power supply. The VBB pin, an internally generated voltage supply, is available to this device only. For single-ended input conditions, the unused differential input is connected to VBB as a switching reference voltage. VBB may also rebias AC coupled inputs. When used, decouple VBB and VCC via a 0.01 mF capacitor and limit current sourcing or sinking to 0.5 mA. When not used, VBB should be left open. The 100 Series contains temperature compensation.
Features
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MC100 EP195B AWLYYWWG LQFP-32 FA SUFFIX CASE 873A 32 1
1
1
32
MC100 EP195B ALYWG
QFN32 MN SUFFIX CASE 488AM A WL, L Y, YY W, WW G = Assembly Location = Wafer Lot = Year = Work Week = Pb-Free Package
*For additional marking information, refer to Application Note AND8002/D.
ORDERING INFORMATION
See detailed ordering and shipping information in the package dimensions section on page 15 of this data sheet.
* * * * * *
Maximum Input Clock Frequency >1.2 GHz Typical Programmable Range: 0 ns to 10 ns Delay Range: 2.2 ns to 12.2 ns 10 ps Increments PECL Mode Operating Range: VCC = 3.0 V to 3.6 V with VEE = 0 V NECL Mode Operating Range: VCC = 0 V with VEE = -3.0 V to -3.6 V
1
* IN/IN Inputs Accept LVPECL, LVNECL, LVDS Levels * A Logic High on the EN Pin Will Force Q to Logic Low * D[10:0] Can Select Either LVPECL, LVCMOS, or * *
LVTTL Input Levels VBB Output Reference Voltage These are Pb-Free Devices
(c) Semiconductor Components Industries, LLC, 2008
September, 2008 - Rev. 1
Publication Order Number: MC100EP195B/D
MC100EP195B
VEE D7 32 D8 D9 D10 IN IN VBB VEF VCF 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 MC100EP195B D8 D9 D10 IN IN VBB VEF VCF
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16
D6 31
32
D5 30
D4 29
D3 27
D2
D1
28
26
25 24 23 22 21 20 19 18 17 16
VEE D0 VCC Q Q VCC VCC NC
Figure 1. 32-Lead LQFP Pinout (Top View)
VEE
Figure 1. 32-Lead QFN (Top View)
LEN D7 VEE
31
SETMIN LEN
SETMAX D5
30
VCC
CASCADE
CASCADE
EN
VEE
D6
MC100EP195B
D4
29
D3
27
D2
D1
28
26
25 24 23 22 21 20 19 18 17
VEE D0 VCC Q Q VCC VCC NC
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SETMIN
SETMAX
VCC
CASCADE
CASCADE
EN
Exposed Pad (EP)
MC100EP195B
Table 1. PIN DESCRIPTION
Pin 23, 25, 26, 27, 29, 30, 31, 32, 1, 2 3 4 5 6 7 8 9, 24, 28 Name D[0:9] I/O LVCMOS, LVTTL, ECL Input LVCMOS, LVTTL, ECL Input LVPECL, LVDS LVPECL, LVDS - - - - Default State Low Description Single-Ended Parallel Data Inputs [0:9]. Internal 75 kW to VEE. (Note 1) Single-Ended CASCADE/CASCADE Control Input. Internal 75 kW to VEE. (Note 1) Noninverted Differential Input. Internal 75 kW to VEE. Inverted Differential Input. Internal 75 kW to VEE and 36.5 kW to VCC. ECL Reference Voltage Output Reference Voltage for ECL Mode Connection LVCMOS, ECL, OR LVTTL Input Mode Select Negative Supply Voltage. All VEE Pins must be Externally Connected to Power Supply to Guarantee Proper Operation. (Note 2) Positive Supply Voltage. All VCC Pins must be externally Connected to Power Supply to Guarantee Proper Operation. (Note 2) Single-ended D pins LOAD / HOLD input. Internal 75 kW to VEE. Single-ended Minimum Delay Set Logic Input. Internal 75 kW to VEE. (Note 1) Single-ended Maximum Delay Set Logic Input. Internal 75 kW to VEE. (Note 1) Inverted Differential Cascade Output for D[10]. Typically Terminated with 50 W to VTT = VCC - 2 V. Noninverted Differential Cascade Output. for D[10] Typically Terminated with 50 W to VTT = VCC - 2 V. Single-ended Output Enable Pin. Internal 75 kW to VEE. No Connect. The NC Pin is Electrically Connected to the Die and "MUST BE" Left Open Noninverted Differential Output. Typically Terminated with 50 W to VTT = VCC - 2 V. Inverted Differential Output. Typically Terminated with 50 W to VTT = VCC - 2 V.
D[10] IN IN VBB VEF VCF VEE
Low Low High - - - -
13, 18, 19, 22
VCC
-
-
10 11 12 14 15 16 17 21 20
LEN SETMIN SETMAX CASCADE CASCADE EN NC Q Q
ECL Input ECL Input ECL Input ECL Output ECL Output ECL Input - ECL Output ECL Output
Low Low Low - - Low - - -
1. SETMIN will override SETMAX if both are high. SETMAX and SETMIN will override all D[0:10] inputs. 2. All VCC and VEE pins must be externally connected to Power Supply to guarantee proper operation.
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MC100EP195B
Table 2. CONTROL PIN
Pin EN State LOW (Note 3) Function Input Signal is Propagated to the Output
HIGH
LEN LOW (Note 3) HIGH SETMIN LOW (Note 3) HIGH SETMAX LOW (Note 3) HIGH D10 LOW (Note 3) HIGH
Output Holds Logic Low State
Transparent or LOAD mode for real time delay values present on D[0:10]. LOCK and HOLD mode for delay values on D[0:10]; further changes on D[0:10] are not recognized and do not affect delay. Output Delay set by D[0:10] Set Minimum Output Delay Output Delay set by D[0:10] Set Maximum Output Delay CASCADE Output LOW, CASCADE Output HIGH CASCADE Output LOW, CASCADE Output HIGH
3. Internal pulldown resistor will provide a logic LOW if pin is left unconnected.
Table 3. CONTROL D[0:10] INTERFACE VCF VCF
VCF VEF Pin (Note 4) No Connect 1.5 V $ 100 mV ECL Mode LVCMOS Mode LVTTL Mode (Note 5)
4. Short VCF (pin 8) and VEF (pin 7). 5. When Operating in LVTTL Mode, the reference voltage can be provided by connecting an external resistor, RCF (suggested resistor value is 2.2 kW $5%), between VCF and VEE pins.
Table 4. DATA INPUT ALLOWED OPERATING VOLTAGE MODE TABLE
CONTROL DATA SELECT INPUTS PINS (D [0:10]) POWER SUPPLY PECL Mode Operating Range NECL Mode Operating Range LVCMOS YES N/A LVTTL YES N/A LVPECL YES N/A LVNECL N/A YES
Table 5. ATTRIBUTES
Characteristics Internal Input Pulldown Resistor ESD Protection (R1) Human Body Model Machine Model Charged Device Model Value 75 kW > 2 kV > 100 V > 2 kV Pb-Free Pkg Level 1 Level 2 UL 94 V-0 @ 0.125 in 1217 Devices
Moisture Sensitivity, Indefinite Time Out of Drypack (Note 6) QFN-32 LQFP-32 Flammability Rating Oxygen Index: 28 to 34 Transistor Count Meets or exceeds JEDEC Spec EIA/JESD78 IC Latchup Test 6. For additional information, see Application Note AND8003/D.
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IN 512 GD* 1 1 1 1 1 1 1 1 256 GD* 128 GD* 64 GD* 32 GD* 16 GD* 8 GD* 4 GD*
0 2 GD*
0
0
0
0
0
0
0
0 1 1 GD*
0 1 1 GD*
0 1
R1
Q Q
IN
EN
R1
R1
LEN R1 10 BIT LATCH R1 R1 R1 D8 D7 D6 D5 D4 R1 R1 R1 R1 D9 R1 D3
SET MIN
Figure 2. Logic Diagram
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CASCADE Latch CASCADE D10 R1
MC100EP195B
5
SET MAX R1 D2 R1 D1 R1 D0 R1
VBB
VCF
VEF *GD = (GATE DELAY) APPROXIMATELY 10 ps DELAY PER GATE (MINIMUM FIXED DELAY APPROX. 2.2 ns)
VEE
MC100EP195B
Table 6. THEORETICAL DELAY VALUES
D(9:0) Value XXXXXXXXXX 0000000000 0000000001 0000000010 0000000011 0000000100 0000000101 0000000110 0000000111 0000001000 0000010000 0000100000 0001000000 0010000000 0100000000 1000000000 1111111111 XXXXXXXXXX *Fixed minimum delay not included. SETMIN H L L L L L L L L L L L L L L L L L SETMAX L L L L L L L L L L L L L L L L L H Programmable Delay* 0 ps 0 ps 10 ps 20 ps 30 ps 40 ps 50 ps 60 ps 70 ps 80 ps 160 ps 320 ps 640 ps 1280 ps 2560 ps 5120 ps 10230 ps 10240 ps
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MC100EP195B
14000 13000 12000 11000 10000 9000 DELAY ( ps) 8000 7000 6000 5000 4000 3000 2000 1000 0 0 100 200 300 400 500 600 700 800 900 1000 VCC = 0 V VEE = -3.3 V 25C 85C
-40C
Decimal Value of Select Inputs (D[9:0])
Figure 3. Measured Delay vs. Select Inputs
Table 7. MAXIMUM RATINGS
Symbol VCC VEE VI Iout IBB TA Tstg qJA qJC qJA qJC Tsol Parameter Positive Mode Power Supply Negative Mode Power Supply Positive Mode Input Voltage Negative Mode Input Voltage Output Current VBB Sink/Source Operating Temperature Range Storage Temperature Range Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Thermal Resistance (Junction-to-Ambient) Thermal Resistance (Junction-to-Case) Wave Solder 0 lfpm 500 lfpm 2S2P Standard Board 0 lfpm 500 lfpm 2S2P Standard Board <2 to 3 sec @ 248C QFN-32 QFN-32 QFN-32 LQFP-32 LQFP-32 LQFP-32 Condition 1 VEE = 0 V VCC = 0 V VEE = 0 V VCC = 0 V Continuous Surge VI VCC VI VEE Condition 2 Rating 6 -6 6 -6 50 100 0.5 -40 to +85 -65 to +150 31 27 12 80 55 12 to 17 265 265 Unit V V V V mA mA mA C C C/W C/W C/W C/W C/W C/W C
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect device reliability.
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MC100EP195B
Table 8. 100EP DC CHARACTERISTICS, PECL VCC = 3.3 V, VEE = 0 V (Note 7)
-40C Symbol IEE VOH VOL VIH Characteristic Negative Power Supply Current Output HIGH Voltage (Note 8) Output LOW Voltage (Note 8) Input HIGH Voltage (Single-Ended) LVPECL CMOS TTL Input LOW Voltage (Single-Ended) LVPECL CMOS TTL ECL Output Voltage Reference LVTTL Mode Input Detect Voltage Reference Voltage for ECL Mode Connection Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 9) Input HIGH Current (@ VIH) Input LOW Current (@ VIL) Min 90 2155 1355 2075 2000 2000 1355 0 0 1775 1.4 1900 1.2 0 0 1875 1.5 2020 Typ 115 2280 1480 Max 170 2405 1605 2420 3300 3300 1675 800 800 1975 1.6 2150 3.3 150 150 Min 100 2155 1355 2075 2000 2000 1490 0 0 1775 1.4 1900 1.2 0 0 1875 1.5 2020 25C Typ 140 2280 1480 Max 170 2405 1605 2420 3300 3300 1675 800 800 1975 1.6 2150 3.3 150 150 Min 100 2155 1355 2075 2000 2000 1490 0 0 1775 1.4 1900 1.2 0 0 1875 1.5 2020 85C Typ 145 2280 1480 Max 170 2405 1605 2420 3300 3300 1675 800 800 1975 1.6 2150 3.3 150 150 Unit mA mV mV mV
VIL
mV
VBB VCF VEF VIHCMR IIH IIL
mV V mV V mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 7. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -0.3 V. 8. All loading with 50 W to VCC - 2.0 V. 9. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC100EP195B
Table 9. 100EP DC CHARACTERISTICS, NECL VCC = 0 V, VEE = -3.3 V (Note 10)
-40C Symbol IEE VOH VOL VIH VIL VBB VEF VIHCMR Characteristic Negative Power Supply Current (Note 11) Output HIGH Voltage (Note 12) Output LOW Voltage (Note 12) Input HIGH Voltage (Single-Ended) LVNECL Input LOW Voltage (Single-Ended) LVNECL ECL Output Voltage Reference Reference Voltage for ECL Mode Connection Input HIGH Voltage Common Mode Range (Differential Configuration) (Note 13) Input HIGH Current (@ VIH) Input LOW Current (@ VIL) Min 90 -1145 -1945 -1225 -1945 -1525 -1400 VEE+ 1.2 0 0 -1425 -1280 Typ 115 -1020 -1820 Max 170 -895 -1695 -880 -1625 -1325 -1250 0.0 Min 100 -1145 -1945 -1225 -1945 -1525 -1400 VEE+ 1.2 0 0 -1425 -1280 25C Typ 140 -1020 -1820 Max 170 -895 -1695 -880 -1625 -1325 -1250 0.0 Min 100 -1145 -1945 -1225 -1945 -1525 -1400 VEE+ 1.2 0 0 -1425 -1280 85C Typ 145 -1020 -1820 Max 170 -895 -1695 -880 -1625 -1325 -1250 0.0 Unit mA mV mV mV mV mV mV V
IIH IIL
150 150
150 150
150 150
mA mA
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 10. Input and output parameters vary 1:1 with VCC. VEE can vary +0.3 V to -0.3 V. 11. Required 500 lfpm air flow when using +5 V power supply. For (VCC - VEE) > 3.3 V, 5 W to 10 W in line with VEE required for maximum thermal protection at elevated temperatures. Recommend VCC - VEE operation at 3.8 V. 12. All loading with 50 W to VCC - 2.0 V. 13. VIHCMR min varies 1:1 with VEE, VIHCMR max varies 1:1 with VCC. The VIHCMR range is referenced to the most positive side of the differential input signal.
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MC100EP195B
Table 10. AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 14)
-40C Symbol fmax VoutPP tPLH tPHL Characteristic Maximum Frequency Output Voltage Amplitude Propagation Delay IN to Q; D(0-10) = 0, SETMIN IN to Q; D(0-10) = 1023, SETMAX EN to Q; D(0-10) = 0 D0 to CASCADE Programmable Range tPD (max) - tPD (min) Step Delay (Note 15) D0 High D1 High D2 High D3 High D4 High D5 High D6 High D7 High D8 High D9 High 610 2000 10900 1990 375 Min Typ 1.2 820 2400 12400 2500 475 2800 13900 2990 575 610 2150 11500 2130 400 Max Min 25C Typ 1.2 820 2500 13000 2600 500 2950 14500 3130 600 610 2250 12250 2380 425 Max Min 85C Typ 1.2 820 2700 13750 2800 525 3050 15250 3380 625 Max Unit GHz mV ps
tRANGE Dt
8950
9950 10 16 32 65 155 310 620 1200 2500 4900
10950
9450
10450 11 18 33 72 165 325 650 1300 2600 5200
11450
10110
11100
12110 15 26 46 92 195 370 720 1400 2800 5500
ps ps
NLIN
Non-Linearity (Note 21) 0 to 511 Decimal Values for D[9:0] Range 512 to 1024 Decimal Values for D[9:0] Range 1 to 1023 Decimal Values for D[9:0] Range Duty Cycle Skew (Note 16) Setup Time |tPHL-tPLH| 200 500 300 200 400 300 400 350
ps $7.0 $7.0 $11 25 -40 -550 100 50 -320 -150 180 220 0.9 1.9 2.0 5.0 90 200 500 300 200 400 300 400 350 $7.0 $7.0 $11 25 -40 -590 100 40 -350 -170 200 250 1.1 2.6 2.0 5.0 90 200 500 300 200 400 300 400 350 $11 $11 $18 25 -40 -650 120 30 -400 -200 210 260 1.2 3.3 2.0 5.0 90 ps ps
tSKEW ts
D to LEN D to IN (Note 17) EN to IN (Note 18) LEN to D IN to EN (Note 19) EN to IN (Note 20) SET MAX to LEN SET MIN to LEN
th
Hold Time
ps
tR
Release Time
ps
tjitter
RMS Random Clock Jitter @ 1.2 GHz IN to Q; D(0:10) = 0 or SETMIN IN to Q; D(0:10) = 1023 or SETMAX
ps
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. 15. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range. 16. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. 17. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set. 18. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than 75 mV to that IN/IN transition. 19. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than 75 mV to that IN/IN transition. 20. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified IN to Q propagation delay and transition times. 21. Deviation from a linear delay (actual Min to Max) in the 1024 programmable steps.
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MC100EP195B
Table 10. AC CHARACTERISTICS VCC = 0 V; VEE = -3.0 V to -3.6 V or VCC = 3.0 V to 3.6 V; VEE = 0 V (Note 14)
-40C Symbol VPP tr tf Characteristic Input Voltage Swing (Differential Configuration) Output Rise/Fall Time @ 50 MHz 20-80% (Q) 20-80% (CASCADE) Min 150 Typ 800 Max 1200 Min 150 25C Typ 800 Max 1200 Min 150 85C Typ 800 Max 1200 Unit mV ps
85 110
115 160
140 210
100 120
120 175
140 230
100 120
130 190
165 250
NOTE: Device will meet the specifications after thermal equilibrium has been established when mounted in a test socket or printed circuit board with maintained transverse airflow greater than 500 lfpm. Electrical parameters are guaranteed only over the declared operating temperature range. Functional operation of the device exceeding these conditions is not implied. Device specification limit values are applied individually under normal operating conditions and not valid simultaneously. 14. Measured using a 750 mV source, 50% duty cycle clock source. All loading with 50 W to VCC - 2.0 V. 15. Specification limits represent the amount of delay added with the assertion of each individual delay control pin. The various combinations of asserted delay control inputs will typically realize D0 resolution steps across the specified programmable range. 16. Duty cycle skew guaranteed only for differential operation measured from the cross point of the input to the cross point of the output. 17. This setup time defines the amount of time prior to the input signal the delay tap of the device must be set. 18. This setup time is the minimum time that EN must be asserted prior to the next transition of IN/IN to prevent an output response greater than 75 mV to that IN/IN transition. 19. This hold time is the minimum time that EN must remain asserted after a negative going IN or positive going IN to prevent an output response greater than 75 mV to that IN/IN transition. 20. This release time is the minimum time that EN must be deasserted prior to the next IN/IN transition to ensure an output response that meets the specified IN to Q propagation delay and transition times. 21. Deviation from a linear delay (actual Min to Max) in the 1024 programmable steps. IN VINPP = VIH(D) - VIL(D) IN Q VOUTPP = VOH(Q) - VOL(Q) Q tPHL tPLH
Figure 4. AC Reference Measurement
Cascading Multiple EP195Bs To increase the programmable range of the EP195B, internal cascade circuitry has been included. This circuitry allows for the cascading of multiple EP195Bs without the need for any external gating. Furthermore, this capability requires only one more address line per added E195B. Obviously, cascading multiple programmable delay chips will result in a larger programmable range: however, this increase is at the expense of a longer minimum delay. Figure 5 illustrates the interconnect scheme for cascading two EP195Bs. As can be seen, this scheme can easily be
expanded for larger EP195B chains. The D10 input of the EP195B is the CASCADE control pin. With the interconnect scheme of Figure 5 when D10 is asserted, it signals the need for a larger programmable range than is achievable with a single device and switches output pin CASCADE HIGH and pin CASCADE LOW. The A11 address can be added to generate a cascade output for the next EP195B. For a 2-device configuration, A11 is not required.
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MC100EP195B
Need if Chip #3 is used
A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
ADDRESS BUS
D7 D8 D9 D10 INPUT IN IN VBB VEF
D6
D5
D4
VEE
D3
D2
D1 VEE D0
D7 D8 D9 D10 IN IN VBB VEF
D6
D5
D4
VEE
D3
D2
D1 VEE D0
EP195B CHIP #2
VCC Q Q VCC VCC CASCADE CASCADE
EP195B CHIP #1
VCC Q Q VCC VCC CASCADE CASCADE OUTPUT
SETMAX
SETMIN
SETMIN
VCF LEN VEE
NC EN
VCF LEN VEE
SETMAX
NC EN BIT 9 D9 Q9 LEN
Set Reset
VCC
Figure 5. Cascading Interconnect Architecture
An expansion of the latch section of the block diagram is pictured in Figure 6. Use of this diagram will simplify the explanation of how the cascade circuitry works. When D10 of chip #1 in Figure 5 is LOW this device's CASCADE output will also be low while the CASCADE output will be high. In this condition the SET MIN pin of chip #2 will be asserted HIGH and thus all of the latches of chip #2 will be reset and the device will be set at its minimum delay. Chip #1, on the other hand, will have both SET MIN and SET MAX deasserted so that its delay will be controlled entirely by the address bus A0--A9. If the delay needed is greater than can be achieved with 1023 gate delays
(1111111111 on the A0--A9 address bus) D10 will be asserted to signal the need to cascade the delay to the next EP195B device. When D10 is asserted, the SET MIN pin of chip #2 will be deasserted and SET MAX pin asserted resulting in the device delay to be the maximum delay. Table 11 shows the delay time of two EP195B chips in cascade. To expand this cascading scheme to more devices, one simply needs to connect the D10 pin from the next chip to the address bus and CASCADE outputs to the next chip in the same manner as pictured in Figure 5. The only addition to the logic is the increase of one line to the address bus for cascade control of the second programmable delay chip.
TO SELECT MULTIPLEXERS
BIT 0 D0 Q0 LEN SET MIN SET MAX
Set Reset
BIT 1 D1 Q1 LEN
Set Reset
BIT 2 D2 Q2 LEN
Set Reset
BIT 3 D3 Q3 LEN
Set Reset
BIT 4 D4 Q4 LEN
Set Reset
BIT 5 D5 Q5 LEN
Set Reset
BIT 6 D6 Q6 LEN
Set Reset
BIT 7 D7 Q7 LEN
Set Reset
VCC
BIT 8 D8 Q8 LEN
Set Reset
Figure 6. Expansion of the Latch Section of the EP195B Block Diagram
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MC100EP195B
Table 11. Delay Value of Two EP195B Cascaded
VARIABLE INPUT TO CHIP #1 AND SETMIN FOR CHIP #2 INPUT FOR CHIP #1 D10 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 D7 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 D6 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 D5 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 D4 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 D3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 D1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 D0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 Delay Value 0 ps 10 ps 20 ps 30 ps 40 ps 50 ps 60 ps 70 ps 80 ps 160 ps 220 ps 640 ps 1280 ps 2560 ps 5120 ps 10230 ps Total Delay Value 4400 ps 4410 ps 4420 ps 4430 ps 4440 ps 4450 ps 4460 ps 4470 ps 4480 ps 4560 ps 4720 ps 5040 ps 5680 ps 6960 ps 9520 ps 14630 ps
VARIABLE INPUT TO CHIP #1 AND SETMAX FOR CHIP #2 INPUT FOR CHIP #1 D10 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 D9 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 D8 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 1 D7 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 D6 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 1 D5 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 1 D4 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 1 D3 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 1 D2 0 0 0 0 1 1 1 1 0 0 0 0 0 0 0 1 D1 0 0 1 1 0 0 1 1 0 0 0 0 0 0 0 1 D0 0 1 0 1 0 1 0 1 0 0 0 0 0 0 0 1 Delay Value 10240 ps 10250 ps 10260 ps 10270 ps 10280 ps 10290 ps 10300 ps 10310 ps 10320 ps 10400 ps 10560 ps 10880 ps 11520 ps 12800 ps 15360 ps 20470 ps Total Delay Value 14640 ps 14650 ps 14660 ps 14670 ps 14680 ps 14690 ps 14700 ps 14710 ps 14720 ps 14800 ps 14960 ps 15280 ps 15920 ps 17200 ps 19760 ps 24870 ps
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MC100EP195B
Multi-Channel Deskewing
The most practical application for EP195B is in multiple channel delay matching. Slight differences in impedance and cable length can create large timing skews within a high-speed system. To deskew multiple signal channels, each channel can
be sent through each EP195B as shown in Figure 7. One signal channel can be used as reference and the other EP195Bs can be used to adjust the delay to eliminate the timing skews. Nearly any high-speed system can be fine-tuned (as small as 10 ps) to reduce the skew to extremely tight tolerances.
EP195B
IN IN #1
Q Q
EP195B IN IN #2 Q Q
EP195B IN IN #N Control Logic Digital Data Q Q
Figure 7. Multiple Channel Deskewing Diagram Measure Unknown High Speed Device Delays
EP195Bs provide a possible solution to measure the unknown delay of a device with a high degree of precision. By combining two EP195Bs and EP31 as shown in Figure 8, the delay can be measured. The first EP195B can be set to SETMIN and its output is used to drive the unknown delay device, which in turn drives the input of a D flip-flop of EP31. The second EP195B is triggered along with the first EP195B and its output provides a clock signal for EP31. The programmed delay of the second EP195B is varied to detect the output edge from the unknown delay device.
CLOCK CLOCK EP195B IN IN #1 Q Q
If the programmed delay through the second EP195B is too long, the flip-flop output will be at logic high. On the other hand, if the programmed delay through the second EP195B is too short, the flip-flop output will be at a logic low. If the programmed delay is correctly fine-tuned in the second EP195B, the flip-flop will bounce between logic high and logic low. The digital code in the second EP195B can be directly correlated into an accurate device delay.
Unknown Delay Device D EP31 Q
EP195B IN IN #2 Q Q
CLK
Q
Control Logic
Figure 8. Multiple Channel Deskewing Diagram
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MC100EP195B
Q Driver Device Q Zo = 50 W 50 W 50 W D Zo = 50 W D Receiver Device
VTT VTT = VCC - 2.0 V
Figure 9. Typical Termination for Output Driver and Device Evaluation (See Application Note AND8020/D - Termination of ECL Logic Devices.)
ORDERING INFORMATION
Device MC100EP195BFAG MC100EP195BFAR2G MC100EP195BMNG MC100EP195BMNR4G Package LQFP-32 (Pb-Free) LQFP-32 (Pb-Free) QFN-32 (Pb-Free) QFN-32 (Pb-Free) Shipping 250 Units / tray 2000 / Tape & Reel 74 Units / Rail 1000 / Tape & Reel
For information on tape and reel specifications, including part orientation and tape sizes, please refer to our Tape and Reel Packaging Specifications Brochure, BRD8011/D.
Resource Reference of Application Notes
AN1405/D AN1406/D AN1503/D AN1504/D AN1568/D AN1642/D AND8001/D AND8002/D AND8020/D AND8066/D AND8090/D - ECL Clock Distribution Techniques - Designing with PECL (ECL at +5.0 V) - ECLinPSt I/O SPiCE Modeling Kit - Metastability and the ECLinPS Family - Interfacing Between LVDS and ECL - The ECL Translator Guide - Odd Number Counters Design - Marking and Date Codes - Termination of ECL Logic Devices - Interfacing with ECLinPS - AC Characteristics of ECL Devices
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MC100EP195B
PACKAGE DIMENSIONS
32 LEAD LQFP CASE 873A-02 ISSUE C
A
25 4X
A1
32
0.20 (0.008) AB T-U Z
-T-, -U-, -Z-
1
BASE METAL
-T- B B1
8
-U- V DETAIL Y
17
P F AE DETAIL Y
V1
9
9
-Z- S1 S
4X
0.20 (0.008) AC T-U Z
8X M_
SECTION AE-AE R
G -AB-
SEATING PLANE
DETAIL AD
CE
-AC- 0.10 (0.004) AC
GAUGE PLANE
X DETAIL AD
NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DATUM PLANE -AB- IS LOCATED AT BOTTOM OF LEAD AND IS COINCIDENT WITH THE LEAD WHERE THE LEAD EXITS THE PLASTIC BODY AT THE BOTTOM OF THE PARTING LINE. 4. DATUMS -T-, -U-, AND -Z- TO BE DETERMINED AT DATUM PLANE -AB-. 5. DIMENSIONS S AND V TO BE DETERMINED AT SEATING PLANE -AC-. 6. DIMENSIONS A AND B DO NOT INCLUDE MOLD PROTRUSION. ALLOWABLE PROTRUSION IS 0.250 (0.010) PER SIDE. DIMENSIONS A AND B DO INCLUDE MOLD MISMATCH AND ARE DETERMINED AT DATUM PLANE -AB-. 7. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. DAMBAR PROTRUSION SHALL NOT CAUSE THE D DIMENSION TO EXCEED 0.520 (0.020). 8. MINIMUM SOLDER PLATE THICKNESS SHALL BE 0.0076 (0.0003). 9. EXACT SHAPE OF EACH CORNER MAY VARY FROM DEPICTION. MILLIMETERS MIN MAX 7.000 BSC 3.500 BSC 7.000 BSC 3.500 BSC 1.400 1.600 0.300 0.450 1.350 1.450 0.300 0.400 0.800 BSC 0.050 0.150 0.090 0.200 0.450 0.750 12_ REF 0.090 0.160 0.400 BSC 1_ 5_ 0.150 0.250 9.000 BSC 4.500 BSC 9.000 BSC 4.500 BSC 0.200 REF 1.000 REF INCHES MIN MAX 0.276 BSC 0.138 BSC 0.276 BSC 0.138 BSC 0.055 0.063 0.012 0.018 0.053 0.057 0.012 0.016 0.031 BSC 0.002 0.006 0.004 0.008 0.018 0.030 12_ REF 0.004 0.006 0.016 BSC 1_ 5_ 0.006 0.010 0.354 BSC 0.177 BSC 0.354 BSC 0.177 BSC 0.008 REF 0.039 REF
DIM A A1 B B1 C D E F G H J K M N P Q R S S1 V V1 W X
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0.250 (0.010)
H
W
K
Q_
EE EE EE EE
J
AE
N D
0.20 (0.008)
M
AC T-U Z
MC100EP195B
PACKAGE DIMENSIONS
QFN32 5x5, 0.5 P CASE 488AM-01 ISSUE O
A B
NOTES: 1. DIMENSIONS AND TOLERANCING PER ASME Y14.5M, 1994. 2. CONTROLLING DIMENSION: MILLIMETERS. 3. DIMENSION b APPLIES TO PLATED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 MM TERMINAL 4. COPLANARITY APPLIES TO THE EXPOSED PAD AS WELL AS THE TERMINALS. MILLIMETERS MIN NOM MAX 0.800 0.900 1.000 0.000 0.025 0.050 0.200 REF 0.180 0.250 0.300 5.00 BSC 2.950 3.100 3.250 5.00 BSC 2.950 3.100 3.250 0.500 BSC 0.200 --- --- 0.300 0.400 0.500
D
PIN ONE LOCATION
2X 2X
0.15 C 0.15 C 0.10 C
32 X
0.08 C L
32 X
32 X b 0.10 C A B
0.05 C BOTTOM VIEW 0.28
32 X
ECLinPS is a trademark of Semiconductor Components Industries, LLC.
ON Semiconductor and are registered trademarks of Semiconductor Components Industries, LLC (SCILLC). SCILLC reserves the right to make changes without further notice to any products herein. SCILLC makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does SCILLC assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages. "Typical" parameters which may be provided in SCILLC data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. SCILLC does not convey any license under its patent rights nor the rights of others. SCILLC products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the SCILLC product could create a situation where personal injury or death may occur. Should Buyer purchase or use SCILLC products for any such unintended or unauthorized application, Buyer shall indemnify and hold SCILLC and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that SCILLC was negligent regarding the design or manufacture of the part. SCILLC is an Equal Opportunity/Affirmative Action Employer. This literature is subject to all applicable copyright laws and is not for resale in any manner.
PUBLICATION ORDERING INFORMATION
LITERATURE FULFILLMENT: Literature Distribution Center for ON Semiconductor P.O. Box 5163, Denver, Colorado 80217 USA Phone: 303-675-2175 or 800-344-3860 Toll Free USA/Canada Fax: 303-675-2176 or 800-344-3867 Toll Free USA/Canada Email: orderlit@onsemi.com N. American Technical Support: 800-282-9855 Toll Free USA/Canada Europe, Middle East and Africa Technical Support: Phone: 421 33 790 2910 Japan Customer Focus Center Phone: 81-3-5773-3850 ON Semiconductor Website: www.onsemi.com Order Literature: http://www.onsemi.com/orderlit For additional information, please contact your local Sales Representative
EE EE
TOP VIEW SIDE VIEW
9 8
E
(A3) A A1 C
EXPOSED PAD 16 SEATING PLANE
DIM A A1 A3 b D D2 E E2 e K L
SOLDERING FOOTPRINT*
5.30 3.20 0.63
32 X
D2
K
17 32 X
E2
1 32 25 24
e
3.20 5.30
0.50 PITCH
DIMENSIONS: MILLIMETERS
28 X
*For additional information on our Pb-Free strategy and soldering details, please download the ON Semiconductor Soldering and Mounting Techniques Reference Manual, SOLDERRM/D.
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MC100EP195B/D

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